The initial funding for Center Domain-Specific Computing (CDSC) was provided by the National Science Foundation under the Expedition in Computing Program. Intel Corporation become the first industrial partner to provide financial support of CDSC under the InTrans (Innovation Transitions) Program and the CAPA (Programming for Heterogeneous Architectures) Program together with the NSF.
CDSC is actively seeking additional partners from the industry and other research organizations. The current partners are listed below.
Industrial Partners
Companies interested in becoming a partner of CDSC are welcome to contact the CDSC Director, Prof. Jason Cong.
Partner Benefits
- Seat on the CDSC Industry Advisory Board
- Sponsoring and participating in joint research projects
- Sending company representatives to work on campus with CDSC faculty and students
- Licensing rights to CDSC technologies
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AMD |
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Cadence |
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Jump Trading |
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Qualcomm |
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Siemens DIS |
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Synopsys |
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TSMC, Ltd. |
Other Financial Contributions include:
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Amazon.com, Inc. |
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Google LLC |
Biographies of CDSC Advisory Board Members
| Name | Title | Affiliation | |
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Stephen Neuendorffer | Fellow | AMD |
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Paul Cunningham | Senior Vice President and General Manager of the System Verification Group | Cadence
Design Systems |
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Darko Kirovski | Quant, JCS Group | Jump Trading |
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Durga Malladi | Senior Vice President & General Manager, Technology Planning, Edge Solutions & Data Center | Qualcomm Technologies, Inc. |
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Juan Rey | Vice-president of government programs | Siemens |
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Prith Banerjee | SVP Simulation and Analysis Incubation | Synopsys |
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Lee-Chung Lu | Vice President of Research & Development/Design & Technology Platform | TSMC |
Stephen Neuendorffer is a Fellow in the AMD Research and Development Group
working on early development of compilation for compute acceleration, focused on leveraging LLVM and MLIR. Previously, he was product architect of Xilinx Vivado HLS, co-authored a widely used textbook on HLS design for FPGAs, and worked with customers on a wide variety of applications, including video encoders, computer vision, wireless systems, and networking systems. He received B.S. degrees in Electrical Engineering and Computer Science from the University of Maryland, College Park in 1998. He graduated with University Honors, Departmental Honors in Electrical Engineering, and was named the Outstanding Graduate in the Department of Computer Science. He received the Ph.D. degree from the University of California, Berkeley in 2005, after being one of the key architects of Ptolemy II.
Paul Cunningham is senior vice president and general manager of the system verification group at Cadence Design Systems. His product responsibilities include logic simulation, emulation, prototyping, formal, VIP, and debug. Prior to this, he was responsible for Cadence’s frontend digital design tools including logic synthesis and design-for-test. Paul joined Cadence in 2011 through the acquisition of Azuro, a startup developing concurrent physical optimization and useful skew clock tree synthesis technologies, where he was a co-founder and CEO. Paul holds a Master’s Degree and a Ph.D. in Computer Science from the University of Cambridge, UK.
Darko Kirovski graduated from UCLA’s CS department with a PhD in VLSI CAD in 2000. After spending 12 years at Microsoft Research where he split his time between the crypto and machine learning teams, in 2011 he joined as a quant Jump Trading’s jcs group, the largest market maker in the world across many asset classes. As an academic he has published numerous conference and journal articles in several fields of computer science and electrical engineering, and is an inventor on over 100 US patents. As a quant, he has been a member of a team that has married machine learning and statistics with high performance computing and world spanning networking in order to bring market making into the modern age.
Durga Malladi is Senior Vice President and General Manager, Technology Planning, Edge Solutions & Data Center, at Qualcomm Technologies, Inc. He joined as a Senior Engineer in 1998.
He is responsible for technology product management and roadmap planning across all businesses in Qualcomm Technologies. This spans artificial intelligence (hardware, software, tools), connectivity (5G, Wi-Fi, Bluetooth, Satellite Communications, positioning), processors (CPU, GPU, NPU), multimedia (computer vision, audio, video, sensors), central software, developer ecosystem, and data management and analytics platforms. In addition, he is responsible for Qualcomm’s cellular infrastructure and data center businesses.
In prior roles from 2006-18, Durga led wireless research in Qualcomm including 4G LTE/LTE-Advanced and 5G enhanced Mobile Broadband (eMBB), Ultra Reliable Low Latency Communications (URLLC), and Massive IoT, spanning sub6 and mmW bands. His responsibilities spanned system design, standardization, prototype testbeds, pre-commercial vendor inter-operability tests and trials.
Durga is a senior member of IEEE and holds 517 USPTO granted patents. He is a recipient of Qualcomm’s IP Excellence Award, Qualcomm Distinguished Contributor Award for Project Leadership, Qualcomm Upendra Patel Achievement Awards for Outstanding Contributions, and Distinguished Alumnus Award from Indian Institute of Technology, Madras. He serves on the CTIA Board of Directors and the AI Governance Alliance Steering Committee at the World Economic Forum.
Durga holds a B.Tech (’93) from Indian Institute of Technology, Madras, M.S (’95) and Ph.D. (’98) from UCLA, and an AI Graduate Certificate from Stanford (’23). His Ph.D. dissertation is on adaptive estimation and filtering techniques, and his research interests include artificial intelligence, signal processing, communication theory, and quantum computing.
Juan Rey is Vice-president of government programs at Siemens EDA. He was previously the Senior Engineering Director for the Calibre product line in the Design to Silicon Division at Mentor Graphics Corporation. His group is responsible for the architecture, design and development of Mentor’s software product line for integrated circuit physical verification and tape out tasks such as design rule checking, layout vs. schematic verification, capacitance, resistance and inductance extraction, resolution enhancement, mask data preparation and design for manufacturing. Juan has 30 years of software development experience ranging from research activities at Stanford University (EE department), to development and management of electronic design automation and process and device modeling software at Technology Modeling Associates, Cadence and Mentor Graphics. Juan also represents his company at the Executive Technology Advisory Board of Semiconductor Research Corporation (SRC) and is responsible for the IP portfolio and research initiatives of his division.
Prith Banerjee is SVP Simulation and Analysis Incubation at Synopsys. He was Chief Technology Officer at ANSYS, a leader in engineering simulation. Prior to that, he was CTO of Schneider Electric, CTO of ABB, Managing Director of R&D at Accenture, and Director of HP Labs. Previously he spent 20 years in academia as Professor, Chairman and Dean at the University of Illinois and Northwestern University. Banerjee currently serves on the Board of Directors of Turntide Technologies. In the past, he has served on the Board of Cray, CUBIC. and Anita Borg Institute, and the Technical Advisory Boards of Ambit, Atrenta, Calypto, Cypress, Ingram Micro, and Virsec. He is a Fellow of the AAAS, ACM and IEEE. He received a B.Tech. in electronics engineering from the Indian Institute of Technology, Kharagpur, and an M.S. and Ph.D. in electrical engineering from the University of Illinois, Urbana.
Lee-Chung Lu
Dr. L.C. Lu is Vice President of Research & Development / Design & Technology Platform at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and a TSMC Fellow. Dr. Lu is responsible for supporting design enablement to meet a wide range of requirements from the Company’s broad customer base. Prior to this role, he served as function head of Design and Technology Platform from 2018. Since joining TSMC in 2000, Dr. Lu held a number of management roles related to design services. Dr. Lu collaborated with process RD to innovate Design and Technology Co-Optimization (DTCO) to enhance speed, power and density for TSMC’s new process technologies. He has worked closely with design ecosystem partners through the TSMC Open Innovation Platform® (OIP) to provide comprehensive design solutions and IPs to enable high density, high performance, automotive, RF, 2.5D and 3D designs for different customer applications.
In 2012, Dr. Lu received Taiwan’s National Outstanding Manager Award and was elected as a TSMC Fellow. He is one of TSMC’s most prolific inventors with more than 100 patents in the United States and other countries. Dr. Lu received his B.S. in Electrical Engineering from National Taiwan University, M.S. in Computer Science from National Tsing Hua University, and Ph.D. in Computer Science from Yale University.