The core funding for Center Domain-Specific Computing (CDSC) is provided by the National Science Foundation under the Expedition in Computing Program. CDSC is actively seeking partners from the industry and other research organizations.
Companies interested in becoming a partner of CDSC are welcome to contact the CDSC Director, Prof. Jason Cong.
- Seat on the CDSC Industry Advisory Board
- Sponsoring and participating in joint research projects
- Sending company representatives to work on campus with CDSC faculty and students
- Licensing rights to CDSC technologies
Biographies of CDSC Advisory Board Members
|Ivo Bolsens||CTO and Senior VP||Xilinx|
|Ziang Hu||VP of Huawei America Research Center
Head of Software Lab
CTO of Huawei Central Software Institute
|Geoff Lowney||Senior Fellow, Software & Solutions Group
Chief Technology Officer, Developer Products Division
|Juan Rey||Senior Engineering Director Calibre Design to Silicon Division||Mentor Graphics|
Ivo Bolsens is senior vice president and chief technology officer (CTO), with responsibility for advanced technology development, Xilinx research laboratories (XRL) and Xilinx university program (XUP). Dr. Bolsens came to Xilinx in June 2001 from the Belgium-based research center IMEC, where he was vice president of information and communication systems. His research included the development of knowledge-based verification for VLSI circuits, design of digital signal processing applications, and wireless communication terminals. He also headed the research on design technology for high-level synthesis of DSP hardware, HW/SW co-design and system-on-chip design. Bolsens holds a PhD in applied science and an MSEE from the Catholic University of Leuven in Belgium.
Ziang Hu has 30 years industry and academia experience in compilers, operating systems, parallel and distributed computing, SW/HW co-design, performance optimization and etc. He holds positions in Huawei America Research Center, NVidia, University of Delaware, Temple University, and NUDT. Currently, Dr. Hu is VP of Huawei America Research Center, Head of Software Lab, CTO of Huawei Central Software Institute, and Huawei Fellow. He is leading the infrastructure software effort in Huawei cross mobile devices, networking devices, and data center solutions.
Geoff Lowney is an Intel Senior Fellow in the Software and Services Group and serves as chief technology officer for the Developer Products Division at Intel Corporation. He directs the development of compilers, run-time systems and programming tools for Intel platforms. He was appointed an Intel Fellow in 2001 for his leadership in compiler and architecture advanced development, then elevated to Senior Fellow in 2015. In 2008, Lowney was named an Association for Computing Machinery (ACM) Fellow for his contributions to compiler technology and performance-enhancement tools. Lowney joined Intel as part of a 2001 agreement that transferred Compaq Computer Corporation’s microprocessor engineering and design expertise to Intel. Before joining Intel, he was a Compaq Fellow and the director of compiler and architecture advanced development for Compaq’s Alpha Microprocessor Group. Lowney was also a member of the Alpha microprocessor group at Digital Equipment Corporation (DEC), which later became a part of Compaq. Before joining DEC in 1991, Lowney was a consulting engineer at Hewlett-Packard Company as well as a leader of the compiler team at Multiflow Computer. He started his career as an assistant professor at the Courant Institute of Mathematical Sciences at New York University. Lowney earned his bachelor’s degree in mathematics from Yale University and his master’s degree and Ph.D. in computer science, also from Yale. He has been granted nearly 20 patents in computer architecture and compiler technology, with additional patents pending.
Juan Rey is the Senior Engineering Director for the Calibre product line in the Design to Silicon Division at Mentor Graphics Corporation. His group is responsible for the architecture, design and development of Mentor’s software product line for integrated circuit physical verification and tape out tasks such as design rule checking, layout vs. schematic verification, capacitance, resistance and inductance extraction, resolution enhancement, mask data preparation and design for manufacturing. Juan has 30 years of software development experience ranging from research activities at Stanford University (EE department), to development and management of electronic design automation and process and device modeling software at Technology Modeling Associates, Cadence and Mentor Graphics. Juan also represents his company at the Executive Technology Advisory Board of Semiconductor Research Corporation (SRC) and is responsible for the IP portfolio and research initiatives of his division.