Partners

The core funding for Center Domain-Specific Computing (CDSC) is provided by the National Science Foundation under the Expedition in Computing Program.  CDSC is actively seeking  partners from the industry and other research organizations.


Industrial Partners


Companies interested in becoming a partner of CDSC are welcome to contact the CDSC Director, Prof. Jason Cong.

      Partner Benefits

  • Seat on the CDSC Industry Advisory Board
  • Sponsoring and participating in joint research projects
  • Sending company representatives to work on campus with CDSC faculty and students
  • Licensing rights to CDSC technologies
 
Biographies of CDSC Advisory Board Members

Name

Title

Affiliation

Ivo Bolsens

CTO and Senior VP

Xilinx

Nicholas Ilyadis

Vice president and CTO of Broadcom’s Infras- tructure and Networking Group (ING)

Broadcom

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Norm Jouppi

Fellow and Director of Exascale Computing Lab

HP

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Gerhard Laub

Director of the company’s Magnetic Resonance Research & Development

Siemens

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Jaime Moreno

 

Senior Manager, Microprocessor Architecture

IBM Research

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Stephen Pawlowski

Senior Fellow and CTO of Intel Architecture Group

Intel

 

Ivo Bolsens is senior vice president and chief technology officer (CTO), with responsibility for advanced technology development, Xilinx research laboratories (XRL) and Xilinx university program (XUP). Dr. Bolsens came to Xilinx in June 2001 from the Belgium-based research center IMEC, where he was vice president of information and communication systems. His research included the development of knowledge-based verification for VLSI circuits, design of digital signal processing applications, and wireless communication terminals. He also headed the research on design technology for high-level synthesis of DSP hardware, HW/SW co-design and system-on-chip design. Bolsens holds a PhD in applied science and an MSEE from the Catholic University of Leuven in Belgium.

Nicholas (Nick) Ilyadis serves as vice president and CTO of Broadcom’s Infrastructure and Networking Group (ING), responsible for product strategy and cross portfolio initiatives for a broad portfolio of chip products that include network switch, Ethernet controllers, Enterprise WLAN, SerDes, PHY, processors and security. Prior to Broadcom, Ilyadis served as vice president of Engineering for Enterprise Data Products at Nortel Networks. He has also held various engineering positions at Digital Equipment Corporation and Itek Optical Systems. Ilyadis holds a MSEE from the University of New Hampshire and a BTEE from the Rochester Institute of Technology.

Norman P. Jouppi is a fellow and director of the Intelligent Infrastructure Lab at HP Labs, the company’s central research and development arm, overseeing research on building next-generation hardware and software compute infrastructure using a cross-layer inter-disciplinary approach.

Jouppi is well-known for his innovations in computer memory systems, including stream prefetch buffers, victim caching, multi-level exclusive caching and development of the CACTI tool for modeling cache timing, area and power. His research innovations have been adopted in microprocessors from most high-performance microprocessor vendors.

He has also been the principal architect and lead designer of several microprocessors, contributed to the architecture and design of graphics accelerators, and extensively researched video, audio and physical telepresence. His recent work includes implications of emerging nanophotonic technology on computer systems, low-latency high-bandwidth networking for cluster computing, heterogeneous chip multiprocessor architectures, and blade system architectures. Jouppi joined HP in 2002 from Compaq Computer Corp., where he was a staff fellow at Compaq’s Western Research Laboratory in Palo Alto, Calif. From 1984 through 1996, he was a consulting assistant/associate professor in the department of electrical engineering at Stanford University, where he taught classes in VLSI, circuits and computer architecture.

Jouppi received his Ph.D. in electrical engineering from Stanford University in 1984, and a master of science in electrical engineering from Northwestern University in 1980. While at Stanford, he was one of the principal architects and designers of the MIPS microprocessor, as well as a developer of techniques for CMOS VLSI timing verification.

He currently serves as past chair of ACM Special Interest Group on Computer Architecture (SIGARCH), is on the ACM Council and on the Computing Research Association (CRA) board. He is on the editorial board of Communications of the ACM and IEEE Computer Architecture Letters, and is a fellow of the ACM and the IEEE. He holds more than 34 U.S. patents. He has published over 100 technical papers, with several best paper awards and one Symposium on Computer Architecture (ISCA) Influential Paper Award.

Gerhard Laub Employed by Siemens Medical Solutions for over two decades, Dr. Laub is currently the director of the company’s Magnetic Resonance Research & Development West component based in San Francisco.  For many years, he has also served as a visiting professor in UCLA’s Department of Radiology.

Dr. Laub received his Ph.D from University of Stuttgart, Germany in 1981.  His field of study is coded aperture imaging, optical image processing.  As a multi-dimensional program director, Dr. Laub is known internationally for his expertise and contributions in magnetic resonance imaging.  During his lengthy career he has collaborated closely with clinicians, scientists and developers to explore innovative clinical applications and provide better imaging techniques to patients around the world.

Dr. Laub has been honored by the European Society for Magnetic Resonance in Medicine and Biology for contributions to basic and applied research in medical magnetic resonance.  He is a fellow of the International Society for Magnetic Resonance in Medicine and is the recipient of their gold medal award for pioneering time-of-flight techniques for three-dimensional MR angiography.

Jaime H. Moreno is Senior Manager, Microprocessor Architecture, at the IBM Thomas J. Watson Research Center in New York. He joined the IBM Research Division in 1992, where he has performed research on a variety of microprocessor architecture and performance analysis topics, including high-end server microprocessors, game processors, low-power embedded processors and digital signal processors. In his current role as Senior Manager, he leads a department whose research activities include power/reliability aware microarchitectures, systems technology and microarchitecture interactions, advanced systems architecture, and advanced compiler technology. His department's efforts address the full range of IBM processors and systems.

In addition to multiple publications in journals and conferences, Jaime is coauthor of the books "Introduction to Digital Systems" (Wiley, 1999) and "Matrix Computations on Systolic-Type Arrays (Kluwer, 1992). He holds 17 patents in processor architecture, has been recognized as Master Inventor at IBM Research, and is member of the IBM Academy of Technology.

Before joining IBM Research, Jaime was a faculty member at the Department of Electrical Engineering, University of Concepcion, Chile. He received his Ph.D. and M.S. degrees in Computer Science from the University of California Los Angeles, and a degree in Electrical Engineering from the University of Concepcion, Chile.

Stephen S. Pawlowski is an Intel Senior Fellow. He is the Digital Enterprise Group Chief Technology Officer and General Manager for Architecture and Planning for Intel Corporation.

Pawlowski joined Intel in 1982. He led the design of the first Multibus I Single Board Computer based on the 386 processor. He was a lead architect and designer for Intel's early desktop PC and high performance server products and was the co-architect for Intel's first P6 based server chipsets. He helped define the system bus interfaces for Intel's P6 family processors, the Pentium® 4 processor and Itanium™ processor. He also created and led the research for Intel's agile radio architecture for a future generation of wireless products and prior to his current assignment was the director of Corporate Technology Group's Microprocessor Technology Lab.

Pawlowski graduated from the Oregon Institute of Technology in 1982 with bachelor's degrees in electrical engineering technology and computer systems engineering technology, and received a master's degree in computer science and engineering from the Oregon Graduate Institute in 1993. Pawlowski holds 56 patents in the area of system, and microprocessor technologies. He has received three Intel Achievement Awards.

 

Other Research Partners on Campus