Upcoming Events

CDSC/InTrans Project Annual Review Meeting, February 27-28, 2020

Day 1: California Room, UCLA Faculty Center, 480 Charles E Young Dr E, Los Angeles, CA 90095

Day 2: Shannon Room, 54-134 Engineering IV

February 27, 2020 California Room, UCLA Faculty Center

8:00am-8:30am Breakfast

8:30am-9:10am Opening Session

Welcome Remarks, Jayathi Murthy, Dean, UCLA HSSEAS

Center Overview, Jason Cong, UCLA CS/ECE

9:10am-9:55am Keynote Speech: New tools to measure neuronal dynamics in models of neurological disease, Peyman Golshani, Professor and John Mazziotta Chair in Neurology, UCLA

9:55am-10:15am Break

10:15am-11:40am Application Drivers for Customizable Computing

╶ Thrust Overview, Alex Bui, UCLA Radiology

╶ Acceleration of calcium imaging processing pipeline for the UCLA miniscope project, Zhe Chen, UCLA CS

╶ Computationally efficient and accurate 3D network for enhancing low-dose CT image quality, Leihao Wei, UCLA Radiology

╶ Hardware Acceleration for Multi-Modal Human-Robot Communication, Song-Chun Zhu, UCLA Statistics

╶ OpenPose acceleration and end-to-end optimization for deep learning, Atefeh Sohrabizadeh, UCLA CS

11:40am-1:00pm Lunch

1:00pm-1:50pm Keynote Speeches:

Versal: The Xilinx Adaptive Compute Acceleration Platform (ACAP) with AI engines , Dr. Kees Vissers, Xilinx Fellow

Vitis Unified Software Platform, Thomas Bollaert, Sr. Technical Director, Xilinx

1:50pm-3:15pm Architectures for Customizable Computing

– Thrust Overview, Glenn Reinman, UCLA CS

– Programmable Accelerator Synthesis, Sihao Liu, UCLA CS

– A High-Performance Adaptive Merge Tree Architecture for Sorting, Weikang Qiao UCLA ECE

– StreamFloating: Leveraging Rich Stream Semantics in Cache Hierarchy, Zhengrong Wang, UCLA CS

– ReACH: Reconfigurable Accelerator Compute Hierarchy, Glenn Reinman, UCLA CS

3:15pm-3:35pm Break

3:35pm-5:00pm Compilation and Design Automation

– Thrust Overview, Vivek Sarkar, Georgia Tech

– Neural Network-based Operators for Graph Search, Yizhou Sun, UCLA CS

– Marvel: Accelerating Convolutions of DNN Models on Spatial Accelerators, Prasanth Chatarasi, Georgia Tech, CS

– Data-Specific Compilation for Sparse Structures, Louis-Noel Pouchet, Colorado State Univ., CS & ECE

– Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency, Jason Lau, UCLA CS

5:00pm-5:15pm Posters Introduction

5:30pm-8:00pm Poster session + reception – Sequoia Room, UCLA Faculty Center

 

February 28, 2020 Shannon Room, 54-134 Engineering IV (No Food& Drink Allowed)

8:00am-8:30am Breakfast – Tesla Room 53-125 Engineering IV

Special sessions on NSF/Intel Partnership on Computer Assisted Programming for Heterogeneous Architectures (CAPA)

8:30am-10:10am HeteroCL and associated compilation technologies

– CAPA Project Overview, Jason Cong, UCLA CS

– Building FPGA-targeted Accelerators with HeteroCL, Zhiru Zhang, Cornell ECE

– Latest advances in systolic array compilation, Jie Wang, UCLA CS

– HeteroRefactor: Refactoring for Heterogeneous Computing with FPGA, Qian Zhang and Jason Lau, UCLA CS

– Predictable Accelerator Design, Adrian Sampson, Cornell CS

10:10am-10:30am Break – Tesla Room 53-125 Engineering IV

10:30am-11:10am HeteroCL

– HeteroHalide — from Halide to FPGAs, Yuze Chi, UCLA CS

– Create a formal ISA spec and generate the architecture design correct-by-construction using HeteroCL , Jin Yang, Intel Labs (Invited talk)

11:10am-12:00pm Industrial feedback session

12:00pm-1:30pm Lunch – Tesla Room 53-125 Engineering IV

– CDSC Advisory Board Meeting, Tannas Alumni Room, 176 EVI, (CDSC industrial advisory board members only, 12:00pm-1:30pm )

 

KEYNOTE/INVITED SPEAKERS

Speaker: Peyman Golshani, UCLA Professor and Chair in Neurology and in the Semel Institute for NeuroScience

Title: New tools to measure neuronal dynamics in models of neurological disease

Biography

Peyman Golshani is a Professor and John Mazziotta chair in Neurology and in the Semel Institute for Neuroscience. Dr. Golshani completed his MD/PhD at UC Irvine under the direction of the late Dr. Edward G. Jones. He completed a neurology residency at UCLA and was appointed Assistant Professor in 2006. His laboratory studies the neuronal network dynamics that drive cognition and how these coordinated patterns of activity become corrupted in models of neurodevelopmental disorders.

Speaker: Kees Vissers, Xilinx Fellow

Title: Versal: The Xilinx Adaptive Compute Acceleration Platform (ACAP) with AI engines

Abstract

In this presentation I will present the new Adaptive Compute Acceleration Platform. I will show the overall system architecture of the family of devices including the Arm cores (scalar engines), the programmable logic (Adaptable Engines) and the new vector processor cores (AI engines). I will focus on the new AI engines in more detail and show the architecture, the integration in the total device, the programming environment and some applications, including Machine Learning and 5G wireless applications. The latest Silicon device contains 400 of these novel vector processor cores.

Biography

Kees Vissers graduated from Delft University in the Netherlands. He worked at Philips Research in Eindhoven, the Netherlands, for many years. The work included Digital Video system design, HW –SW co-design, VLIW processor design and dedicated video processors. He was a visiting industrial fellow at Carnegie Mellon University, where he worked on early High Level Synthesis tools. He was a visiting industrial fellow at UC Berkeley where he worked on several models of computation and dataflow computing. He was a director of architecture at Trimedia, and CTO at Chameleon Systems. For more than a decade he is heading a team of researchers at Xilinx. The research topics include next generation programming environments for processors and FPGA fabric, high-performance video systems, machine learning applications and architectures, wireless applications and datacenter applications. He has been instrumental in the High-Level Synthesis technology and one of the technical leads in the novel array of AI engines. He is now a Fellow at Xilinx.

Speaker: Thomas Bollaert, Sr. Technical Director, Xilinx

Title: Vitis Unified Software Platform

Abstract

Recently, Xilinx introduced a new heterogeneous compute architecture, the Adaptive Compute Acceleration Platform (ACAP), with significantly more flexibility and performance to address an evolving set of new applications such as machine learning. This advancement on the device side is accompanied by similar advances on higher-level programming approaches to make FPGAs and ACAPs significantly easy to use for a wide range of applications. Xilinx Vitis Unified Software Platform is a comprehensive development environment to build and seamlessly deploy accelerated applications on Xilinx platforms including Alveo cards, FPGA-instances in the cloud, and embedded platforms. Vitis AI, an integral part of Vitis, enables AI inference acceleration on Xilinx platforms including Alveo cards, FPGA-instances in the cloud, and embedded platforms. Vitis addresses the three major industry trends: the need for heterogenous computing, applications that span cloud to edge to end-point, and AI proliferation. In this talk, we will provide an overview of Vitis and Vitis AI development environments.

Biography

Thomas Bollaert is a Senior Technical Director at Xilinx, driving the evolution and the adoption of the FPGA acceleration tool flow. Thomas is passionate about realizing the full potential of FPGAs as acceleration platforms, in the cloud as well as on-premise. He has a deep background in hardware design flows, including more than 10 years of experience with High-Level Synthesis. He has accumulated experience in technology, marketing and management and has a track record of helping companies worldwide move through strategic changes to increase competitiveness. Prior to Xilinx, Thomas was a VP of Application Engineering at Calypto Design Systems and began his career as a hardware designer in France.

Speaker: Jin Yang, Intel Corp.

Title: Create a formal ISA spec and generate the architecture design correct-by-construction using HeteroCL

Biography

Dr. Jin Yang is a Principal Engineer in Intel Labs’ Strategic CAD Labs, responsible for driving research on hardware and software validation and high-assurance system design. Jin received his Ph.D. degree in Computer Science from the University of Texas at Austin in 1997 where his research interest was on formal specification and verification of real time systems.

 

LIST OF POSTERS

Architectures for Customizable Computing

A High-Performance Adaptive Merge Tree Architecture for Sorting — Weikang Qiao, Nikola Samardzic, Mau-Chung Frank Chang, Jason Cong

Acceleration of Graph Processing through Decoupled-task Execution — Vidushi Dadu, Tony Nowatzki

FLASH: Fast, ParalleL, and Accurate Simulator for HLS — Young-kyu Choi, Yuze Chi, Jie Wang, Yuan Zhou, Jason Cong

Offloading Protobuf Transformations — Mrunal Patel, Jason Cong

Evaluation and Analysis of HLS-Based Designs on HBM2 FPGA Boards — Young-kyu Choi, Yuze Chi, Licheng Guo, and Jason Cong

StreamFloating: Leveraging Rich Stream Semantics in Cache Hierarchy — Zhengrong Wang, Tony Nowatzki

Runtime, Compilation, and Design Automation

Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency — Licheng Guo*, Jason Lau*, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong

HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration — Jiajie Li, Yuze Chi, Jason Cong

End-to-End Optimization of Deep Learning Applications — Atefeh Sohrabizadeh, Jie Wang, Jason Cong

HeteroRefactor: Refactoring for Heterogeneous Computing with FPGA — Jason Lau*, Aishwarya Sivaraman*, Qian Zhang*, Muhammad Ali Gulzar, Jason Cong, Miryung Kim

PolySA+:Towards General Systolic Array Compilation — Jie Wang, Jason Cong

Accelerating Convolutions of DNN Models on Spatial Accelerators (Marvel/MAESTRO) — Prasanth Chatarasi,Hyoukjun Kwon, Tushar Krishna, Vivek Sarkar

Optimality Study of Existing Quantum Computing Layout Synthesis Tools — Bochen Tan, Jason Cong

Application Acceleration with Customizable Computing

Layer-Dependent Importance Sampling for Training Deep and Large Graph Convolutional Networks — Difan Zou, Ziniu Hu, Yewen Wang, Song Jiang, Yizhou Sun, Quanquan Gu

Learning-based Efficient Graph Similarity Computation via Multi-Scale Convolutional Set Mathing — Yunsheng Bai, Hao Ding, Yizhou Sun, Wei Wang

Computationally efficient and accurate 3D network for enhancing low-dose CT image quality — Leihao Wei, William Hsu

Accelerating high-scale image to graph neuroimaging kernels — Karl Marrett, Yuze Chi, Zhe Chen, Muye Zhu, Chris Park, William Yang, Jason Cong

Acceleration of Calcium Imaging Processing Pipeline for the UCLA Miniscope Project — Zhe Chen, Garrett Blair, Hugh T. Blair, Jason Cong

VLSI circuit factorization through Graph Matching Neural Network/Graph Matching Neural Networks — Feng Shi, Yuze Chi, Ziheng Xu, Song-Chun Zhu, Jason Cong

Profiling Benchmarking and of a Video Analytics and 3D Scene Reconstruction Platform — Feng Shi, Siyuan Huang, Yixin Zhu, Song-Chun Zhu

Massively Parallel and Scalable Multi-GPU Material Point Method — Xinlei Wang, Yuxing Qiu, Stuart R. Slattery, Yu Fang, Minchen Li, Song-Chun Zhu, Min Tang, Dinesh Manocha, Chenfanfu Jiang

Past Events

• CDSC/InTrans Project Annual Review Meeting, February 28-March 1, 2019

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• CDSC/InTrans Project Semi-Annual Review Meeting – Day One

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• Protected: CDSC Annual Review 2016

  There is no excerpt because this is a protected post.

  January 20, 2016 - January 21, 2016