June 6, 2022 – Day 1: 8:00am-8:00pm, Cohen Multipurpose Room 134 Engineering VI (West & East) – No Food & Drink Allowed.

June 7, 2022 – Day 2: 8:00am-2:00pm, Cohen Multipurpose Room 134 Engineering VI (West & East) – No Food & Drink Allowed.

Day 1 (June 6, 2022)

8:00am-8:30am          Breakfast (First Floor Patio and Breezeway, Engineering VI)

8:30am-8:50am          Welcome and CDSC Overview; Jason Cong, UCLA CS/ECE

Session 1: Customizable Architectures (Chair: Tony Nowatzki, UCLA CS)

8:50am-9:10am        Enabling Programmer-transparent Near-data Computing by Rethinking Memory Abstractions”, Tony Nowatzki, UCLA CS

9:10am-9:30am          TaskStream: Unified Task Dataflow Architecture for Accelerating Task Parallel workloads, Vidushi Dadu, UCLA CS

9:30am-9:50am          hlsSPARSE: Accelerating Sparse Linear Algebra on HBM-based FPGAs with High-Level Synthesis, Linghao Song, UCLA CS

9:50am-10:10am        Accelerating Sorting on HBM-based FPGAs, Weikang Qiao, UCLA CS

10:10am-10:30am     Coffee Break (First Floor Patio and Breezeway, Engineering VI)

Session 2: Keynote Speech 1 and more Customizable Architectures

10:30am-11:10am     Keynote 1: Dataflow Computing for Future Compute Workloads, Ivo Bolsens, CTO of AMD/Xilinx

11:10am-11:30am     Automated synthesis of systolic arrays with applications to machine learning, Jason Cong, UCLA CS/ECE

11:30am-11:50am     OverGen: Improving FPGA Usability through Domain-specific Overlay Generation, Sihao Liu, UCLA CS

11:50am-12:10pm     Multi-band Signaling for Area/Energy-efficient Inter-Processor/Memory I/Os, Frank Chang, UCLA ECE

12:10pm-1:30pm       Lunch (First Floor Patio and Breezeway, Engineering VI)

1:30pm-1:50pm         Greeting from the leadership from the School of Engineering, Jayathi Murthy, Dean, UCLA HSSEAS

Session 3:  Keynote 2 and Novel Applications (Chair: Yizhou Sun, UCLA CS)

1:50pm-2:30pm         Keynote 2:  Use of AI/Machine Learning and High-Performance Computing in Engineering Simulation and Design, Prith Banerjee, CTO of Ansys

2:30pm-2:50pm         Graph-based Neural ODEs for Learning Dynamical Systems; Yizhou Sun, UCLA CS

2:50pm-3:10pm         Real-Time Position Decoding from Calcium Images for Closed-Loop Feedback, Zhe Chen, UCLA CS

3:10pm-3:30pm         Coffee Break (First Floor Patio and Breezeway, Engineering VI)

Session 4:  More on Novel Applications (Chair: Yizhou Sun, UCLA CS)

3:30pm-3:50pm        The Pursuit of Accurate and Efficient Binary Neural Networks, Yichi Zhang, Cornell ECE

3:50pm-4:10pm         Enhancement and analysis of low-dose computed tomography scans: Advances and computing needs, William Hsu, UCLA Radiology

4:10pm-4:30pm         Automated Accelerator Optimization Aided by Graph Neural Networks, Atefeh Sohrabizadeh, UCLA CS

4:30pm-4:50pm         Poster Introductions

5:00pm-8:00pm         Reception + Poster Session (First Floor Patio and Breezeway, Engineering VI)

Day 2 (June 7, 2022)

8:00am-8:30am          Breakfast (First Floor Patio and Breezeway, Engineering VI)

Session 5: Compilation/Synthesis for Customized Computing (Chair: Zhiru Zhang, Cornell ECE )

8:30am-8:50am        Transpiling C to Heterogeneous HLS Code with Automated Test Generation and Program Repair, Miryung Kim, UCLA CS

8:50am-9:10am          TAPA: End-to-End Framework on Co-optimizing HLS and Physical Design for Rapid Timing Closure of Large-Scale FPGA Designs, Licheng Guo, UCLA CS

9:10am-9:30am          Accelerator Programming for Data Specialization, Zhiru Zhang, Cornell ECE

9:30am-9:50am          Generation and Verification of High-Level Transformations for HLS, Louis-Noel Pouchet, Colorado State Univ. CS

9:50am-10:10am        Opportunities for Reinforcement Learning in Healthcare and its Many Computational Challenges, Alex Bui, UCLA Radiology

10:10am-10:30am     Coffee Break (First Floor Patio and Breezeway, Engineering VI)

Session 6:  Quantum Computing (Chair: Jason Cong, UCLA CS/ECE)

10:30am-11:10am     Invited talk:  A Cloud-based End-to-End Optimizing Quantum Compiler, Yunong Shi, Quantum Computing Scientist, Amazon Braket

11:10am-11:30am     Compilation for Near-Term Quantum Computing: Gap Analysis and Optimal Solution, Daniel Bochen Tan, UCLA CS

11:30am-11:50am     Domain-Specific Quantum Architecture Optimizations, Wan-Hsuan Lin, UCLA CS

11:50am-1:00pm       Lunch (First Floor Patio and Breezeway, Engineering VI)

Session 7:  Feedbacks from Industry Partners

1:00pm-2:00pm         Feedbacks from Industry Partners

Posters

Compilations/Synthesis for Customized Computing

• TAPA: End-to-End Framework on Co-optimizing HLS and Physical Design for Rapid Timing Closure of Large-Scale FPGA Designs, Licheng Guo, UCLA CS
• Heterogeneous Processing Network High-Level Synthesis for Versal ACAPs, Jason Lau, UCLA CS
• Automated Accelerator Optimization Aided by Graph Neural Networks, Atefeh Sohrabizadeh, UCLA CS
• A Versatile Systolic Array for Transposed and Dilated Convolution on FPGA, Suhail Basalama, UCLA CS
• AutoMerlin: Automatic Space Exploration with the Polyhedral Model for HLS, Stephane Pouget, UCLA CS
• Compilation for Near-Term Quantum Computing: Gap Analysis and Optimal Solution, Daniel Bochen Tan, UCLA CS
• StreamVSA: A Framework for Automatic Acceleration of DNNs on FPGA, Suhail Basalama, UCLA CS

Customizable Architectures

• Hardware Aware Neural Architecture Search Using FlexCNN Backbone, Chengdi Cao and Lorenzo Ferretti, UCLA CS
• Fast Streaming Application Processing Using Host Memory, Michael Lo, UCLA CS
• Accelerating Sorting on HBM-based FPGAs, Weikang Qiao, UCLA CS
• Near-Stream Computing: Transparent and General Near-Cache Acceleration, Zhengrong Wang, UCLA CS
• Domain-Specific Quantum Architecture Optimization, Wan-Hsuan Lin, UCLA CS
• Infinity Streams: Enabling Transparent and Automated In-Memory Computing, Christopher Liu, UCLA CS
• TaskStream: Unified Task Dataflow Architecture for Accelerating Task Parallel workloads, Vidushi Dadu, UCLA CS
• OverGen: A Multi-core SoC Implementation for Domain-specific Overlay Generation, Sihao Liu, UCLA CS
• OverGen: Unifying System and Accelerator Design Space Exploration for FPGA Overlays, Dylan Kupsh, UCLA CS
• Synthesizing FPGA Overlay: A Compiler Perspective, Jian Weng, UCLA CS
• Full-system Hardware Generation for Real-time Graph Workloads using Task Parallelism, Tony Nowatzki, UCLA CS

Novel Applications

• Improving GNN-Based Accelerator Design Automation with Meta Learning, Yunsheng Bai, UCLA CS
• Real-Time Position Decoding from Calcium Images for Closed-Loop Feedback, Zhe Chen, UCLA CS
• Large-scale Image Reconstruction for High-Throughput Computational Medicine, Karl Marrett, UCLA CS
• Near-SSD Data Ranking for Accelerated Machine Learning Training, Neha Prakriya, UCLA CS
• Accelerating SMT/SAT with Parallel and Distributed Computing, Jason Kimko, UCLA CS
• Online learning for Spatial-Temporal Tasks, Ziniu Hu, UCLA CS
• SPADE: A Spectral Method for Black-Box Adversarial Robustness Evaluatio, Chenhui Deng, Cornell ECE

Keynote Speeches

Dataflow Computing for Future Compute Workloads

SPEAKER: Ivo Bolsens, CTO of AMD/Xilinx

BIO: Ivo Bolsens is senior vice president and chief technology officer (CTO), with responsibility for advanced hardware and software technology development, including future architecture directions and software stacks to enable emerging opportunities in the fields of machine learning and high-performance computing. Bolsens also leads the Xilinx Open Source Program Office to accelerate solutions for programming Xilinx silicon. And he is responsible for the Xilinx University Program (XUP) to create a thriving, global ecosystem for Xilinx technology in academia.

Bolsens joined Xilinx in June 2001, from Interuniversity Microelectronics Centre (IMEC), an international research center based in Belgium, where he was vice president, Design of Information and Communication Systems, leading the R&D of digital signal processing systems (DSP) for  video applications and wireless communication terminals, as well as the development of compilers for DSP processors and system-on-chip (SOC) design software. During his tenure at IMEC,  he and his team spun-out three successful startups in the field of SOC design tools and wireless systems.

He serves on the advisory boards of IMEC, the Engineering Department of San Jose State University, Santa Clara University, and the Department of Electrical Engineering and Computer Sciences at UC Berkeley. He is also a board member of EvoNexus, a startup technology incubator.

Bolsens holds a master’s in Electrical Engineering and a Ph.D. in Applied Science from the Catholic University of Leuven in Belgium.

Use of AI/Machine Learning and High-Performance Computing in Engineering Simulation and Design, Prith Banerjee, CTO of Ansys

SPEAKER: Prith Banerjee, Chief Technology Officer

ABSTRACT: In the past, engineered products were designed with mechanical and electrical CAD tools, simulated and validated for correctness with CAE tools, prototypes were fabricated and tested, and products were then manufactured at scale in factories.   This process required long product cycles often requiring years to build a new product.  Today, one can use unlimited computing and storage available from the cloud to do generative design to explore 10,000 design choices in near real-time, verify these products accurately through simulation (eliminating the need to build physical prototypes) and manufacture the products using additive manufacturing and factory automation.   In the past, simulation tools were used to model specific physics such as mechanical structures, or fluid dynamics, or electromagnetic interactions by solving second order partial differential equations using numerical methods.   Today the simulation tools are being used to solve multi-physics problems (fluid-structure-electromagnetics interactions) at scale using the most complex solvers. We will discuss how AI/Machine Learning and High-Performance Computing can improve engineering simulation.

BIO: Prith Banerjee is the Chief Technology Officer of ANSYS where he is responsible for leading the evolution of ANSYS’ Technology strategy and championing the company’s next phase of innovation and growth  Formerly, he was Executive Vice President, Chief Technology Officer of Schneider Electric.     Previously, he was Managing Director of Global Technology Research and Development at Accenture. Formerly, he was Chief Technology Officer and Executive Vice President of ABB. Earlier, he was Senior Vice President of Research at HP and Director of HP Labs.  Formerly, he was Dean of the College of Engineering at the University of Illinois at Chicago. Formerly, he was the Walter P. Murphy Professor and Chairman of Electrical and Computer Engineering at Northwestern University. Prior to that, he was Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign.  In 2000, he founded AccelChip, a developer of products for electronic design automation, which was acquired by Xilinx Inc. in 2006.  During 2005-2011, he was Founder, Chairman and Chief Scientist of BINACHIP Inc., a developer of products in electronic design automation.  He was listed in the FastCompany list of 100 top business leaders in 2009.   He is a Fellow of the AAAS, ACM and IEEE, and a recipient of the 1996 ASEE Terman Award and the 1987 NSF Presidential Young Investigator Award. He received a B.Tech. in electronics engineering from the Indian Institute of Technology, Kharagpur, and an M.S. and Ph.D. in electrical engineering from the University of Illinois, Urbana.

Invited Talk

A Cloud-based End-to-End Optimizing Quantum Compiler, Yunong Shi, Amazon Braket

SPEAKER: Yunong Shi, Quantum Computing Scientist

BIO: Yunong Shi is a Quantum Computing Scientist at Amazon Braket, leading the effort in quantum compilation and low-level device control. His research interests lie in quantum compilation, architecture design, and formal verification. He has contributed to numerous quantum software frame- works including Qiskit, Scaffold and his research works are published in top-tier conferences including ASPLOS, ISCA, MICRO, and PLDI.

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