Upcoming Events

Center for Domain-Specific Computing (CDSC) Annual Review

March 7, 2024

Cohen Multipurpose Room, 134 Engineering VI

March 8, 2024

Shannon Room, 54-134 Engineering IV

Day 1 (March 7, 2024)

Cohen Multipurpose Room, 134 Engineering VI (No Food or Drink)

8:00am-8:30am          Breakfast (First Floor Patio and Breezeway, Engineering VI)

8:30am-8:45am          Greeting from the leadership from the School of Engineering, Alissa Park, Dean, UCLA HSSEAS

8:45am-9:00am          Welcome and CDSC Overview; Jason Cong, UCLA CS/ECE

9:00am–9:40am         Keynote Speech 1:  How AI and accelerated computing are transforming EDA, Paul Cunningham, Senior Vice President and General Manager of the System Verification Group, Cadence Design Systems, Inc.

9:40am-10:00am        Coffee Break (First Floor Patio and Breezeway, Engineering VI)

Session 1: ML for EDA, Science, and Medicine (Chair: Yizhou Sun, UCLA CS)

10:00am-10:20am     Robust GNN-based Representation Learning for HLS (Atefeh Sohrabizadeh, UCLA CS)

10:20am-10:40am     Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis (Zongyue Qin, UCLA CS)

10:40am-11:00am     Domain and task transfer for HLS (Brady Ding and Weikai Li, UCLA CS)

11:00am-11:20am     Accurate and Scalable Representation Learning on Computation Graphs (Chenhui Deng, Cornell ECE)

11:20am-11:40am     Neural Dynamics for Science: The Symbiosis of Deep Graph Learning and Differential Equations (Zijie Huang, UCLA CS)

11:40am-12:00pm    Deep learning and medical imaging (Alex Bui and William Hsu, UCLA Radiology)

12:00pm-1:10pm      Lunch (First Floor Patio and Breezeway, Engineering VI)

1:10pm-1:20pm        Greeting from CS Department Chair, Todd Millstein

1:20pm-2:00pm       Keynote Speech 2:  TSMC 3DFabric^TM and die-to-die interconnect, King Ho Tam, TSMC Academician and Deputy Director of Chip Implementation

Session 2: Customizable Architectures (Chair: Tony Nowatzki, UCLA CS)

2:00pm-2:20pm        UniSparse: An Intermediate Language for General Sparse Format Customization (Zhiru Zhang, Cornell ECE)

2:20pm-2:40pm         Sparse Acceleration with High Bandwidth Memory: From Kernels to the Integration with an Industry Software LS-DYNA (Linghao Song, UCLA CS)

2:40pm-3:00pm         Affinity Alloc: Taming Not-So Near-Data Computing (Tony Nowatzki,  UCLA CS)

3:00pm-3:20pm         Reinforcement Learning by Imitation for CGRA Scheduling (Dylan Kupsh,  UCLA CS)

3:20pm-3:40pm          Coffee Break (First Floor Patio and Breezeway, Engineering VI)

Session 3: Acceleration for ML and SAT (Chair: Tony Nowatzki, UCLA CS)

3:40pm-4:00pm          Reconfigurable Data-Streaming Architecture to Enable GPT-in-a-Box (Frank Chang, UCLA ECE)

4:00pm-4:20pm          NeSSA: Near-Storage Data Selection for Accelerated Machine Learning Training (Neha Prakriya, UCLA CS)

4:20pm-4:40pm         SAT-Accel: Hardware Acceleration for Modern Boolean Satisfiability Solving (Michael Kevin Lo, UCLA ECE)

4:40pm-5:00pm        OverNoC: Improving FPGA Overlay Usability using Versal NoC (Sihao Liu, UCLA CS)

5:00pm-5:20pm         Poster Introductions

5:30pm-7:30pm         Reception + Poster Session (First Floor Patio and Breezeway, Engineering VI)

Day 2 (March 8, 2024)

Shannon Room, 54-134 Engineering IV (No Food or Drink)

8:00am-8:30am         Breakfast (Tesla Room, 53-125 Engineering IV)

8:30am-9:10am          Keynote Speech 3: Open Source MLIR Compilers for Versal Ryzen AI SOCs, Stephen Neuendorffer, Fellow, AMD Research and Development Group

Session 4: Compilation/Synthesis for Customized Computing (Chair: Zhiru Zhang, Cornell ECE)

9:10am-9:30am          TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs (Neha Prakriya, UCLA CS)

9:30am-9:50am          NLP based Source-to-Source optimization for accelerator designs (Stéphane Pouget, UCLA CS)

9:50am-10:10am         Formal Verification of Source-to-Source Transformations (Louis-Noël Pouchet, Colorado State)

10:10am-10:30am       Bridging HLS, RTL and more: A composable framework for timing optimizations (Jason Lau, UCLA CS and RapidStream)

10:30am-10:50am     Coffee Break (Tesla Room, 53-125 Engineering IV)

Session 5:  Novel LLM and Quantum Computing (Chair: Jason Cong, UCLA CS/ECE)

10:50am-11:10am     HMT: Hierarchical Memory Transformer for Long Context Language Processing (Zifan He, UCLA CS)

11:10am-11:30am      OLSQ2: Scalable Optimal Layout Synthesis for NISQ Quantum Processors (Wan-Hsuan Lin, UCLA CS)

11:30am-11:50am     Compilation for neutral atom array quantum processor (Daniel Tan, UCLA CS)

11:50am-1:00pm       Lunch (Tesla Room, 53-125 Engineering IV)

Session 6:  Feedbacks from Industry Partners

1:00pm-2:00pm        Feedbacks from Industry Partners

Posters

Customizable Architectures

1. Affinity Alloc: Taming Not-So Near-Data Computing, Zhengrong Wang, UCLA CS
2. OverNoC: Improve FPGA Overlay Usability using Versal NoC, Sihao Liu, UCLA CS
3. SAT-Accel: Hardware Acceleration for Modern Boolean Satisfiability Solving, Michael Lo, UCLA ECE
4. Sparse Acceleration with High Bandwidth Memory: From Kernels to the Integration with an Industry Software LS-DYNA, Linghao Song, UCLA CS
5. LevelST: Stream-based Accelerator for Sparse Triangular Solver on HBM-FPGA, Zifan He, UCLA CS
6. NeSSA: Near-Storage Data Selection for Accelerated ML Training, Neha Prakriya, UCLA CS
7. RELICS: Reinforcement Learning by Imitation for CGRA Scheduling, Dylan Kupsh,  UCLA CS

Compilations/Synthesis for Customized Computing

1. Robust GNN-based Representation Learning for HLS, Atefeh Sohrabizadeh, UCLA CS
2. Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach, Stéphane Pouget, UCLA CS
3. TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs, Neha Prakriya, UCLA CS
4. HLS-MLIR:  Automatic Hardware Acceleration of Transformers for ASIC and FPGA Devices, Suhail Basalama, UCLA CS
5. Coarse-grained Floorplanning for High-frequency HLS Designs using Versal NoC on Multi-die FPGA, Jake Ke, UCLA CS
6. Multilevel Quantum Layout Synthesis, Wan-Hsuan Lin, UCLA CS
7. Compilation for neutral atom array quantum processor, Daniel Tan, UCLA CS
8. SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures, Cristian Tirelli, UCLA CS
9. Formal Verification of Source-to-Source Transformations (Louis-Noël Pouchet and Emily Tucker, Colorado State)

Novel Applications with Machine Learning and Big-Data Processing

1. Scan and Select Exploits Causal and Spatial Sparsity, Karl Marrett, UCLA CS
2. HMT: Hierarchical Memory Transformer for Long Context Language Processing, Zifan He, UCLA CS
3. Sample Efficient Task Transfer Learning for HLS, Brady Ding, UCLA CS
4. Learning Branching Heuristics for SAT using Reinforcement Learning, Chengdi Cao, UCLA CS
5. Structure-driven Clause Learning via UNSAT Cores, Jason Kimko, UCLA CS
6. Incorporating Knowledge of Tissue Composition to Improve Registration of Breast Tomosynthesis Scans, Yunzheng Zhu, UCLA Radiology
7. Methods for Harmonizing Computed Tomography Scans to Improve Downstream Medical Imaging AI Performance, Anil Yadav, UCLA Radiology
8. Data-efficient Domain Transfer Learning for High-level Synthesis, Weikai Li, UCLA CS
9. Generalizing Graph ODE for Learning Complex System Dynamics across Environments”, Zijie Huang, UCLA CS
10. Cross modality program representation learning for electronic design automation with high-level synthesis, Zongyue Qin, UCLA CS

Keynote Speaker bios:

Dr. Paul Cunningham is senior vice president and general manager of the system verification group at Cadence Design Systems. His product responsibilities include logic simulation, emulation, prototyping, formal, VIP, and debug. Prior to this, he was responsible for Cadence’s frontend digital design tools including logic synthesis and design-for-test. Paul joined Cadence in 2011 through the acquisition of Azuro, a startup developing concurrent physical optimization and useful skew clock tree synthesis technologies, where he was a co-founder and CEO. Paul holds a Master’s Degree and a Ph.D. in Computer Science from the University of Cambridge, UK.

Dr. King Ho Tam has been with TSMC since 2009 specializing in electrical sign-off methodology. He has lately been working on enabling efficient and accurate static timing analysis, signal and power integrity sign-off methods for 3DIC with leading EDA companies for internal testchips and design houses, as well as design-technology co-optimization with process R&D to enhance 3DFabric^TM for emerging 3DIC applications. He is currently the deputy director of Chip Implementation CAD Department under Design Technology Platform and has been elected as TSMC Academician in 2023. He has 17 US patents and 5 IEEE publications during his tenure at TSMC. He has graduated from UCLA in 2008 as a PhD in Electrical Engineering.

Dr. Stephen Neuendorffer is a Fellow in the AMD Research and Development Group working on early development of compilation for compute acceleration, focused on leveraging LLVM and MLIR. Previously, he was product architect of Xilinx Vivado HLS, co-authored a widely used textbook on HLS design for FPGAs, and worked with customers on a wide variety of applications, including video encoders, computer vision, wireless systems, and networking systems. He received B.S. degrees in Electrical Engineering and Computer Science from the University of Maryland, College Park in 1998. He graduated with University Honors, Departmental Honors in Electrical Engineering, and was named the Outstanding Graduate in the Department of Computer Science. He received the Ph.D. degree from the University of California, Berkeley in 2005, after being one of the key architects of Ptolemy II.

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