Upcoming Events

Center for Domain-Specific Computing (CDSC) Annual Review

Feb. 26, 2026

James West Alumni Center, Founders’ Room

Feb. 27, 2026

Cohen Multipurpose Room, 134 Engineering VI

Day 1 (Feb. 26, 2026): James West Alumni Center, Founders’ Room

8:00am-8:30am          Breakfast (James West Alumni Center, Founders’ Room and Patio)

8:30am-8:40am          Greeting from the Dean of the School Engineering, Alissa Park

8:40am-8:50am          Greeting from CS Department Chair, Wei Wang

8:50am-9:05am          Welcome and CDSC Overview; Jason Cong, UCLA CS/ECE

9:05am–9:45am         Keynote 1:  Accelerating the Future – AI, Compute and Innovation at Scale, Ralph Wittig, Corporate Fellow, CVP Head of Research & Advanced Development, AMD

9:45am-10:05am        Break (James West Alumni Center, Founders’ Room and Patio)

Session 1: Energy-Efficient Deep Learning Models (Chair: Jason Cong, UCLA CS/ECE)

10:05am-10:20am     LUT-LLM: Efficient Large Language Model Inference with Memory-based Computations (Zifan He, UCLA CS)

10:20am-10:35am     H2MT: Semantic-Hierarchy Aware hierarchical memory transformer, (Maryam Haghifam,UCLA CS)

10:35am-10:50am     Learnable Sketch for Polynomial Kernel Linear attention (Zongyue Qin, UCLA CS)

10:50am-11:05am     Fine-grain Sparse Attention via Attention Bounding Boxes Prediction (Haoran Deng, UCLA CS)

11:05am-11:20am     Compress and Check: Recurrent Context Compression with Dynamic Correction (Zifan He/Jiahao Zhang, UCLA CS)

11:20am-11:40am     Efficient Generative AI Algorithm and System (Hanrui Wang, UCLA CS)

11:40am-12:50pm     Lunch (James West Alumni Center, Founders’ Room and Patio)

Session 2: AI for Science and Chip Design in the Agentic Era (Chair: Yizhou Sun, UCLA CS)

12:50pm-1:05pm       LIFT: LLM-Based Hardware Design via GNN Supervised Fine-Tuning (Neha Prakriya, UCLA CS)

1:05pm-1:20pm         AgRefactor: Agentic Memory Workflow for HLS Refactoring (Brady Ding, UCLA CS)

1:20pm-1:35pm         LLM-DSE: Searching Accelerator Parameters with LLM Agents, (Hanyu Wang, UCLA CS)

1:35pm-1:50pm         FD-Bench: A Modular and Fair Benchmark for Data-driven Fluid Simulation (Haixin Wang, UCLA CS)

1:50pm-2:05pm         Graph Fourier Neural ODEs: Modeling Spatial-temporal Multi-scales in Molecular Dynamics (Fang Sun, UCLA CS)

2:05pm-2:20pm         Flow Field Reconstruction with Sensor Placement Policy Learning (Ruoyan Li, UCLA CS)

2:20pm-2:40pm         Break (James West Alumni Center, Founders’ Room and Patio)

Session 3: Compilation for AI Acceleration  (Chair: Zhiru Zhang, Cornell ECE)

2:40pm-3:00pm         Allo: A Dual-Purpose Framework for Accelerator Design and Programming (Zhiru Zhang, Cornell)

3:00pm-3:15pm         Stream Network Abstraction Towards NPU for Scalability and Heterogeneity (Chengyue Wang, UCLA CS)

3:15pm-3:30pm         Phoenix: MLIR-Based Compiler for Hardware Reuse in Dataflow Synthesis (Stephane Pouget and Suhail Basalama, UCLA CS)

3:30pm-3:45pm         Communication-Aware LLM Algorithm Optimization on Trainium Clusters, Yufan Du, UCLA CS)

3:45pm-4:00pm         Compilation for Qualcomm Snapdragon NPUs (Suhail Basalama, UCLA CS)

4:00pm-4:30pm         Poster Introductions

 5:00pm-8:00pm         Reception + Poster Session (James West Alumni Center, Founders’ Room and Patio)

 

Day 2 (February 27, 2026): Cohen Multipurpose Room,

134 Engineering VI (No Food or Drink)

8:00am-8:30am          Breakfast (First Floor Breezeway and Patio,  Engineering VI)

 8:30am-9:10am          Keynote 2:  Use of AI/ML in EDA and Simulation, Prith Banerjee, SVP of Innovation, Synopsys

Session 4: Customized Accelerators for Efficient AI Inferencing (Chair:Hanrui Wang, UCLA CS)

9:10am-9:25am          Quantum Circuit Synthesis Using Multi-Level Logic Network (Hanyu Wang, UCLA CS)

9:25am-9:40am          Improved parameter initialization for the (local) unitary cluster Jastrow ansatz (Wan-Hsuan Lin, UCLA CS)

9:40am-9:55am          QEC Discovery (Daniel Tan, Harvard)

9:55am-10:10am        Compilation for Quantum Error Correction Code with Product Structure (Adrian Liu, UCLA CS)

 10:10am-10:30am     Coffee Break (First Floor Breezeway and Patio,  Engineering VI)

 

Session 5:  Quantum Computing Compilation and Applications (Chair: Tony Nowatzki, UCLA CS)

 10:30am-10:45am     Efficient RAG on a Commercial Compute-in-SRAM Device (Niansong Zhang, Cornell)

10:45am-11:00am     FlexLLM: Composable HLS Library for Flexible LLM Accelerator Design (Jiahao Zhang, UCLA CS)

11:00am-11:15am     SegFold: Accelerating Sparse GEMM with a Fine-Grained Dynamic Dataflow (Alice Wu, UCLA CS)

11:15am-11:30am     Going Beyond SAT Acceleration, Exploring HW Friendly Heuristics (Jake Ke, UCLA CS/Michael Lo, UCLA ECE)

11:30am-11:45am     MAS-SAT: Synergizing ML-Assisted and Standalone Solvers for SAT Solving (Chengdi Cao, UCLA CS)

11:45am-12:00pm     A Compiler and Hardware Generator for Heterogeneous Reconfigurable Systems (Sihao Liu, UCLA CS)

12:00pm-1:15pm       Lunch (First Floor Breezeway and Patio,  Engineering VI)

Session 6:  Feedbacks from Industry Partners

 1:15pm-2:15pm         Feedbacks from Industry Partners

Posters

Energy-Efficient ML Models and Novel Applications

1. HeuriGym: An Agentic Benchmark for LLM-Crafted Heuristics in Combinatorial Optimization, Jiajie Li, Cornell
2. LUT-LLM: Efficient Large Language Model Inference with Memory-based Computations, Zifan He, UCLA CS
3. AgRefactor: Agentic Memory Workflow for HLS Refactoring, Zijian Ding, UCLA
4. LIFT: LLM-Based Hardware Design via GNN Supervised Fine-Tuning, Neha Prakriya, UCLA
5. MAS-SAT: Synergizing ML-Assisted and Standalone Solvers for SAT Solving, Chengdi Cao, UCLA
6. GNN-NPN: Efficient NPN Classification for Large Functions using Graph Neural Network, Chengdi Cao, UCLA
7. Micro-Architecture-Informed Neural Network for High-Level Synthesis Prediction, Weikai Li, UCLA

AI for Science and Chip Design in the Agentic Era

1. Flow Field Reconstruction with Sensor Placement Policy Learning, Ruoyan Li, UCLA CS
2. AutoSculpt: Reinforcement Learning for CGRA Generation, Dylan Kupsh, UCLA CS

Customizable Heterogeneous Architectures

1. Characterizing and Optimizing Realistic Workloads on a Commercial Compute-in-SRAM Device, Niansong Zhang, Cornell
2. FlexLLM: Composable HLS Library for Flexible LLM Accelerator Design, Jiahao Zhang, UCLA CS
3. Going Beyond SAT Acceleration, Exploring HW Friendly Heuristic, Jake Ke, Michael Lo, UCLA
4. Communication-Aware LLM Algorithm Optimization on Trainium Clusters, Yufan Du, UCLA CS
5. SegFold: Accelerating Sparse GEMM with a Fine-Grained Dynamic Dataflow, Alice Wu, UCLA CS 

Compilations/Synthesis for Heterogeneous Computing and AI Acceleration

1. Phoenix: MLIR-Based Compiler for Hardware Reuse in Dataflow Synthesis – Stéphane Pouget, Suhail Basalama, UCLA CS
2. Matrix Multiplication via Systolic Array on AMD AI Engine, Jason Kimko, UCLA
3. Can Asymmetric Tile Buffering Be Beneficial? Chengyue Wang, UCLA
4. Stream Network Abstraction Towards NPU for Scalability and Heterogeneity. Chengyue Wang, UCLA
5. Generative Heterogeneous Reconfigurable Systems, Sihao Liu, UCLA

Quantum Computing Compilation and Applications 

1. Improved parameter initialization for the (local) unitary cluster Jastrow ansatz, Wan-Hsuan Lin, UCLA CS
2. Quantum Circuit Synthesis Using an Exact T Library, Hanyu Wang, UCLA CS
3. Compilation for Quantum Error Correction Code with Product Structure, Adrian Liu, UCLA CS

 

 BIOs of the keynote speakers

 Ralph Wittig, AMD

Ralph Wittig leads AMD’s Research and Advanced Development organization, driving the company’s long-range technology strategy and innovation agenda. With over 25 years at AMD, he has helped architect many of the company’s most advanced product families, including Instinct™, EPYC™, Versal™, and Ryzen™.

Ralph’s interests span computer architecture, AI accelerators, compilers, programming languages, runtime environments, advanced packaging, and system co-design. Known for his collaborative approach and passion for exploration, he loves to push the boundaries of computing—advancing breakthroughs that shape the future of performance, efficiency, and intelligent systems.

Prith Banerjee, Synopsys

Prith Banerjee is SVP Simulation and Analysis Incubation at Synopsys. He was Chief Technology Officer at ANSYS, a leader in engineering simulation. Prior to that, he was CTO of Schneider Electric, CTO of ABB, Managing Director of R&D at Accenture, and Director of HP Labs. Previously he spent 20 years in academia as Professor, Chairman and Dean at the University of Illinois and Northwestern University.   Banerjee currently serves on the Board of Directors of Turntide  Technologies. In the past, he has served on the Board of Cray, CUBIC. and Anita Borg Institute, and the Technical Advisory Boards of Ambit, Atrenta, Calypto, Cypress, Ingram Micro, and Virsec. He is a Fellow of the AAAS, ACM and IEEE. He received a B.Tech. in electronics engineering from the Indian Institute of Technology, Kharagpur, and an M.S. and Ph.D. in electrical engineering from the University of Illinois, Urbana.

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